1. Field of the Invention
The present invention is related to the error checking and the detection of erroneous address bits in a data processing system, and, in particular, to error checking and detection of such address bit in a pipelined manner.
2. General Background
Error checking and detection of erroneous bits for both data words and addresses are currently implemented in modern data processing systems. Such systems may require multiple ports to allow remote processors to access a common storage module. The present invention provides for single and double bit data and address error checking and for single bit error correction of the data bits in a pipelined manner with a minimum of overhead in terms of hardware and complexity.